Verilog code for Full Adder in different abstraction levels
Verilog code for Full Adder in different abstraction levels:
A Full Adder is a combinational logic circuit which has three inputs and two outputs. It adds the three binary values and gives two outputs sum and carry. These full adders can be cascaded to form an n-bit ripple adder. It is mainly used in ALU to perform arithmetic operations.
The functionality of full adder for different inputs is shown in the below table.
a
|
b
|
c
|
sum
|
carry
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
1
|
1
|
1
|
Design/RTL code:
Now, let’s see the Verilog code to implement the full adder using different abstraction levels.
1. Gate level:
As shown in fig, Full Adder can be designed using one 3-input XOR gate, three 2-input AND gates and one 2-input OR gate
module fa(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire w1,w2,w3;
xor x1(sum,a,b,c);
and a1(w1,a,b);
and a2(w2,b,c);
and a3(w3,a,c);
or o1(carry,w1,w2,w3);
endmodule
2. Full Adder using Half Adders:
As shown in below fig., Full Adder can be implemented by using two HalfAdders and one OR gate.
module fa(a,b,c,sum,carry);
 |
input a,b,c;
output sum,carry;
wire w1,w2,w3;
ha ha1(a,b,w1,w2);
ha ha2(w1,c,sum,w3);
or o1(carry,w2,w3);
endmodule
module ha(a,b,s,ca);
input a,b;
output s,ca;
xor xo1(s,a,b);
and an1(ca,a,b);
endmodule
3. Data Flow level:
In Data flow level outputs are expressed as boolean equations in terms of inputs.
module fa(a,b,c,sum,carry);
input a,b,c;
output sum, carry;
assign sum= a^b^c;
assign carry= a&b | b&c| a&c;
endmodule
4. Behavioural level:
In the Behavioral level, we deal with the behaviour of outputs with inputs, rather internal structure of the model.
module fa(a,b,c,sum,carry);
input a,b,c;
output reg sum,carry;
always@(a,b,c)
begin
{carry,sum}=a+b+c;
end
endmodule
Test Bench:
For above all design RTL codes, the following test bench can be applied and verify for different test patterns.
module test();
reg a,b,c;
wire sum,carry;
fa dut (a,b,c,sum,carry);
initial
begin
a=0;b=0;c=0;
#10 a=0;b=0;c=1;
#10 a=0;b=1;c=0;
#10 a=0;b=1;c=1;
#10 a=1;b=0;c=0;
#10 a=1;b=0;c=1;
#10 a=1;b=1;c=0;
#10 a=1;b=1;c=1;
end
initial
$monitor($time,"a=%b,b=%b,c=%b,sum=%b,carry=%b",a,b,c,sum,carry);
initial
#80 $finish;
endmodule
- For the any of the design codes, if we apply above test bench, we will obtain the waveforms as in below fig., I've used Vivado tool to simulate.
 |
| wave forms |
- The results of above simulation are as follows:
0 a=0,b=0,c=0,sum=0,carry=0
10 a=0,b=0,c=1,sum=1,carry=0
20 a=0,b=1,c=0,sum=1,carry=0
30 a=0,b=1,c=1,sum=0,carry=1
40 a=1,b=0,c=0,sum=1,carry=0
50 a=1,b=0,c=1,sum=0,carry=1
60 a=1,b=1,c=0,sum=0,carry=1
70 a=1,b=1,c=1,sum=1,carry=1
- Thank you for visiting.....
- keep on visiting for more codes...please give your valuable feedback....
Comments
Post a Comment