verilog code for shift register IC7495

VERILOG CODE FOR SHIFT REGISTER IC 7495:

      Shift register is a sequential logic circuit, which is used for digital data storage. It consists of a group of flip-flops connected in a chain so that the output from one flip-flop is connected to the input of next flip-flop. All the flip-flops are driven by a common clock, and all are set or reset simultaneously. The fundamental shift registers are classified as Serial In - Serial Out, Serial In - Parallel Out, Parallel In - Serial Out, Parallel In - Parallel Out, and bidirectional shift registers.

IC7495:

• It is a  4-Bit Shift Register with serial and parallel synchronous operating modes. 
• It has one serial input (DS) and four Parallel data inputs(P0-P3) and four parallel data outputs (Q0 - Q3). 
• The serial or parallel mode of operation is controlled by a mode control input (S) and two clock Inputs (CP1) and (CP2). For serial mode, S=0 and for parallel mode, S=1.
• The serial or parallel data transfers occur synchronous with the HIGH to LOW transition of the selected clock input. CP1 is for serial mode and CP2 is for parallel mode.

The Internal Structure and Pin diagram of IC7495 are shown in fig.1 and fig.2 respectively.

Fig.1 Internal structure of IC 7495

 Fig.2 pin diagram of IC 7495

The functional table of IC7495 is as follows:

Table1: Functional Table of IC7495

These details are for the IC 7495 manufactured by MOTOROLA company....

The Design code and Test bench code are given below:

Design Module:

module ic7495(q0,q1,q2,q3,cp1,cp2,s,ds,p0,p1,p2,p3);

input cp1,cp2,s,ds,p0,p1,p2,p3;

output q0,q1,q2,q3;

wire w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;

not n1(w3,s);

not n2(w7,w3);

and and1(w5,w3,cp1);

and and2(w6,cp2,s);

or or1(w8,w5,w6);

aoi a1(w9,ds,w3,w7,p0);

aoi a2(w10,q0,w3,w7,p1);

aoi a3(w11,q1,w3,w7,p2);

aoi a4(w12,q2,w3,w7,p3);

srff ff1(q0,~w9,w9,w8);

srff ff2(q1,~w10,w10,w8);

srff ff3(q2,~w11,w11,w8);

srff ff4(q3,~w12,w12,w8);

endmodule

aoi(o,a,b,c,d);         //code for module aoi 

input a,b,c,d;

output o;

wire w1,w2;

and(w1,a,b);

and(w2,c,d);

nor(o,w1,w2);

endmodule

module srff(q,s,r,clk);        //code for module srff

input s,r,clk;

output reg q;

always@(negedge clk)

begin

    case({s,r})

    2'b00: q=q; 

    2'b01: q=1'b0;

    2'b10: q=1'b1;

    2'b11: q=1'bx;

    endcase

end

endmodule

 Test Bench:

module tb();

reg cp1,cp2,s,ds,p0,p1,p2,p3;

wire q0,q1,q2,q3;

ic7495 dut(q0,q1,q2,q3,cp1,cp2,s,ds,p0,p1,p2,p3);

initial

begin

s=1'b1;

#150 s=1'b0;

end

initial

cp1=1'b0;

always

#10 cp1=~cp1;

initial

cp2=1'b1;

always

#12 cp2= ~cp2;

initial

ds=1'b1;

always

#10 ds= ~ds;

initial

begin

{p0,p1,p2,p3}= 4'b0110;

#25 {p0,p1,p2,p3}= 4'b0100;

#25 {p0,p1,p2,p3}= 4'b1010;

#25 {p0,p1,p2,p3}= 4'b1111;

#25 {p0,p1,p2,p3}= 4'b0000;

#25 {p0,p1,p2,p3}= 4'b1001;

#25 {p0,p1,p2,p3}= 4'b0111;

end

initial

$monitor($time,"s=%b,cp1=%b,cp2=%b,ds=%b,p0=%b,p1=%b,p2=%b,p3=%b,q0=%b,q1=%b,q2=%b,q3=%b,",s,cp1,cp2,ds,p0,p1,p2,p3,q0,q1,q2,q3);

initial

#300 $finish;

endmodule

In above test bench code I've  taken parallel mode (s=1) upto 150 ns and then serial mode(s=0)... 

• The wave form obtained by simulating above design code and test bench in vivado software is

Thank you.......

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