Verilog code for Full Adder in different abstraction levels
     Verilog code for Full Adder in different abstraction levels:     A Full Adder is a combinational logic circuit which has three inputs and two outputs. It adds the three binary values and gives two outputs sum  and carry . These full adders can be cascaded to form an n-bit ripple adder. It is mainly used in ALU to perform arithmetic operations.    The functionality of full adder for different inputs is shown in the below table.            a      b      c      sum      carry         0      0      0      0      0         0      0      1      1      0         0      1      0      1      0         0      1      1      0      1         1      0      0      1      0         1      0      1      0      1         1      1      0      0      1         1      1      1      1      1                                                                 ...